A major reason for the increased production and use of semiconductor devices is attributable to the dramatic reduction in production costs achieved by the electronics industry in converting silicon wafers into a large number of useful chips. By increasing the density of semiconductor devices on a single chip, costs are continually being reduced towards some limit. A great deal of effort has been focused on the design and fabrication of integrated circuits characterized by extremely complex circuitry reduced to a single chip. Such integrated circuits are commonly referred to as Very Large Scale Integration (VLSI) circuits.
The reduction in size and increase in complexity of the integrated circuitry means that ever more semiconductor devices are formed on a single chip in very small size. Principal among such devices are the MOSFETs in all their forms. As dimensions are reduced, a complex set of inter-related structural and electrodynamic problems have surfaced. Such problems arise from the existing electrical properties of semiconductors which are not critical in larger devices spaced further apart in an integrated circuit. These problems include parasitic capacitances and resistances, and punchthrough currents. Undesirable changes in MOSFET response characteristics occur when the source to drain spacing is reduced, especially when reduced below 2 microns, and some current devices use spacings of less than 1 micron. These changes are significant when the depletion regions surrounding the source and drain extend into the silicon substrate under the gate and the depletion regions merge. Reference 2 at pages 298-452 addresses the fabrication of MOSFETs in terms of NMOS, PMOS, and CMOS devices, the disclosure of which is incorporated herein by reference.
Depletion layers are directly affected by the voltage on the device and the substrate doping level. If the depletion layers merge, electric lines of force run directly from the drain to the source through the substrate and a condition called "punchthrough" exists. Punchthrough is evidenced by a current between the source and the drain which is not controlled by the gate. Punchthrough is normally observed when the gate voltage is well below the threshold voltage. It occurs as a result of the widening of the drain depletion region when the reverse-bias voltage on the drain is increased. The electric field of the drain may eventually penetrate into the source region and thereby reduce the potential energy barrier of the source-to-body junction. When this occurs more majority carriers in the source have enough energy to overcome the barrier and an increased current then flows between the source and the body. Some of this current is collected by the drain. In general, punchthrough current begins to dominate the current between the drain and the substrate when the drain and source depletion regions meet. It can be suppressed by keeping the total width of the two depletion regions smaller than the channel width. Thus, punchthrough current flows beneath the surface and is not controlled by the threshold voltage, or the gate voltage in general.
Punchthrough current is a particularly severe problem in short-channel MOSFETs because the source and the drain are closer together and their depletion regions more easily overlap. A means to prevent punchthrough current, which will be discussed further hereinbelow, is to increase the doping of the substrate which tends to decrease the depletion layer widths. However, increased substrate doping causes lower junction breakdown voltages, larger junction capacitance and lower carrier mobilities. Prior to ion implantation, the adjustment of substrate doping was the only practical process to control punchthrough. The lower the doping concentration in the body of the device, the lower the junction capacitance, and lower junction capacitance is in general beneficial.
Thus while the problems here and above described are brought on, in part, by decreasing the distance between the source and the drain (reduction in channel length) the electrical length of a channel can be effectively increased by increasing the distance between the source and the drain depletion regions and this in turn is accomplished by ion implantation under the channel, as well as by other means.
It is believed that a deeper ion implant would reduce the susceptibility of the device to punchthrough, but the question remains as to how to carry out the implantation without increasing the junction capacitance.
Examples of junction capacitance are source-body capacitance and drain-body capacitance. Higher capacitance means longer times to charge and discharge the device and slower switching speed of the logic gates in a MOSIC.
Ion implantation has been widely used to adjust the threshold voltage of the MOSFET. The development of ion implantation for threshold voltage adjustment removed the last obstacle for reliable production of the n-channel devices for MOSICs, because this permits one to choose the body (substrate) doping level without consideration of its impact on the threshold voltage. Thus high performance MOS circuits can be reliable fabricated on lightly-doped substrates. In this technique, implantation of boron, phosphorotis or arsenic ions is made into the regions under the oxide of a MOSFET. The implantation of boron (an acceptor) causes a positive shift in the threshold voltage because there are more holes to drive out of the channel and more holes to recombine with electrons before the n-channel is established. Likewise, P and As give a negative shift to the threshold voltage. Typically, ions are implanted near the surface at less than 0.3 microns below the gate oxide, and they are implanted through the gate oxide layer. This may be followed by an implant-activating anneal which deepens the implant slightly. It is found that 5.times.10.sup.11 ions/cm.sup.2 will shift the threshold voltage by approximately 0.58 V.
Reference 2, at page 342, shows how ion implantation when used to adjust the threshold voltage causes the drain depletion region to be wider in the bulk than it is near the gate oxide interface. As a result, punchthrough current flows below the surface, and consequently, gate voltage has less control over the subthreshold current. Even with enough gate voltage to turn off the channel, punchthrough current can still flow in such devices. An enhancement-mode device which is not turned off when the gate voltage is zero loses its ability to function as a switch.
To prevent punchthrough in short-channel devices the substrate doping can be increased, sometimes called "blanket-doping". This decreases the depletion-layer width but increases the junction capacitance.
To avoid the drawback of blanket doping, an additional boron implant (whose peak concentration is located at a depth near the bottom of the source-drain regions) can be performed. This additional doping reduces the lateral widening of the drain-depletion region below the surface without increasing the doping under the junction regions. With such implants, the punchthrough current can be suppressed to well below the normal drain-substrate current of the device.
If the implant is too shallow, the extra implant will have the effect of shifting the threshold voltage of the device to well beyond a desirable value. If the energy of the ion gun is increased so that the implant is sufficiently deep, the value of drain-substrate current drops to that exhibited by long channel devices. At the same time the surface concentration of dopants remains unchanged so that the threshold voltage is not appreciably shifted.
It would be advantageous to maintain low doping levels in the substrate while controlling punchthrough current. It would be advantageous if implementation technology could be used to provide insulated gate field effects transistors capable of operating at high speed. It would be more advantageous if the MOSFET were also a short channel device without detectable punchthrough current, which is typically difficult to achieve in short channels. It would also be advantageous to avoid high junction capacitance thereby permitting high speed operations of the device. It would be even more advantageous to find a method of fabricating such a transistor by simple means which do not require complex operations.